Matrixed arrays of addressable components are commonly found in applications ranging from computer memories (e.g., random access memory or "RAM") to flat panel video displays including plasma and liquid crystal displays ("LCDs"). The storage elements in a memory unit, or the viewable pixel elements in a display are arrayed in rows and columns. Within the array, each element had a unique address that is specified in terms of horizontal row and vertical column location, e.g., the element at row X, column Y, or element (X,Y).
FIG. 1 depicts a conventional prior art video display 10 as comprising a plurality of pixels (shown as squares) that are arranged along a y-axis in M rows and along an x-axis in N columns. The M.times.N pixels are identifiable by their co-ordinates, e.g., pixel (1,1), pixel (2,1) through pixel (X.sub.M,Y.sub.N).
In the prior art, each pixel in a horizontal row is coupled-together electrically and is driven by a row driver. Thus, the uppermost row of pixels (1,1) through (N,1) is driven by a row driver DX1, the next row of pixels (1,2) through (N,2) is driven by a row driver DX2, and so forth. Similarly, each pixel in a vertical column is coupled together and is driven by a common column driver. Thus, the first vertical column comprising pixels (1,1), (1,2) through (1,X.sub.M) is driven by column driver DY1, and so forth. Thus, one disadvantage of the prior art configuration of FIG. 1 is that an array of M rows and N columns will require M+N drivers. Thus, in a high resolution 1280.times.1024 pixel array, 2,304 separate drivers are required.
In addition to requiring a very large number of drivers, prior art arrays tend to suffer from poor contrast. Assume that pixel (4,7) is to be driven, e.g., is to be "illuminated" or rendered "active". In the prior art scheme shown in FIG. 1, it is necessary to simultaneously cause row driver DX7 to be active, and to cause column driver DY4 to be active. By "active" it is meant that each driver will output a logic level signal that represents an active state, for example a logical level "1" pulse. The only pixel in the array subjected to the combined logic level effects of two pulse trains will be the pixel at the intersection defined by (4,7). Ideally a pixel subjected simultaneously to two pulse train signals is active, whereas all pixels subjected to one or no pulse trains will be inactive. As used herein, it will be understood that the term "driver" refers not merely to the output transistor(s) that physically drive the given row or column, but will also include the source of the logic signals that are output by the driver.
But pixels adjacent to the illuminated pixel tend to become somewhat active due to their exposure to at least one of the pulse trains. For example, pixel (3,7) does not receive a pulse from a column driver, but will receive one logic-level pulse from row driver DX7. The effect is to diminish the "bright/dim" contrast between the desired active pixel and the adjacent pixels.
It is known in the art to enhance the contrast ratio by providing an active dedicated thin film transistor ("TFT") for each pixel in the array. Rather than actively drive an entire row of pixels to activate a single pixel in the row, only the dedicated TFT associated with the target pixel is driven. The resultant so-called "active" (as contrasted with "passive") display exhibits excellent contrast ratio, but is expensive to produce due to the large number of drivers that are required (e.g., M.times.N drivers, or one driver per pixel) and due to the relatively low yield. The active display is essentially a single large integrated circuit measuring perhaps 7.5" (190 mm).times.6.5" (165 mm), and a handful of inoperative pixels in the screen can render the display unacceptable to a user.
There is a need for a mechanism to drive addressable elements in an array that will reduce the total number of drivers required. Further, in a video display environment, such mechanism should enhance the contrast ratio attainable from a passive display without incurring high manufacturing cost and low yield.
The present invention disclosed such a mechanism and a method for driving addressable array elements.